Copyright | (C) 2015-2016, University of Twente |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
Safe Haskell | None |
Language | Haskell2010 |
Documentation
class Backend state where Source #
initBackend, primDir, name, extension, extractTypes, genHDL, mkTyPackage, hdlType, hdlTypeErrValue, hdlTypeMark, hdlSig, genStmt, inst, expr, iwWidth, toBV, fromBV, hdlSyn, mkBasicId, setModName, setSrcSpan, getSrcSpan
initBackend :: Int -> HdlSyn -> state Source #
Initial state for state monad
primDir :: state -> IO FilePath Source #
Location for the primitive definitions
name :: state -> String Source #
Name of backend, used for directory to put output files in. Should be | constant function / ignore argument.
extension :: state -> String Source #
File extension for target langauge
extractTypes :: state -> HashSet HWType Source #
Get the set of types out of state
genHDL :: String -> SrcSpan -> Component -> State state (String, Doc) Source #
Generate HDL for a Netlist component
mkTyPackage :: String -> [HWType] -> State state [(String, Doc)] Source #
Generate a HDL package containing type definitions for the given HWTypes
hdlType :: HWType -> State state Doc Source #
Convert a Netlist HWType to a target HDL type
hdlTypeErrValue :: HWType -> State state Doc Source #
Convert a Netlist HWType to an HDL error value for that type
hdlTypeMark :: HWType -> State state Doc Source #
Convert a Netlist HWType to the root of a target HDL type
hdlSig :: Text -> HWType -> State state Doc Source #
Create a signal declaration from an identifier (Text) and Netlist HWType
genStmt :: Bool -> State state Doc Source #
Create a generative block statement marker
inst :: Declaration -> State state (Maybe Doc) Source #
Turn a Netlist Declaration to a HDL concurrent block
expr :: Bool -> Expr -> State state Doc Source #
Turn a Netlist expression into a HDL expression
iwWidth :: State state Int Source #
Bit-width of IntWordInteger
toBV :: HWType -> Text -> State state Doc Source #
Convert to a bit-vector
fromBV :: HWType -> Text -> State state Doc Source #
Convert from a bit-vector
hdlSyn :: State state HdlSyn Source #
Synthesis tool we're generating HDL for
mkBasicId :: State state (Identifier -> Identifier) Source #
mkBasicId
setModName :: ModName -> state -> state Source #
setModName
setSrcSpan :: SrcSpan -> State state () Source #
setSrcSpan
getSrcSpan :: State state SrcSpan Source #
getSrcSpan