Copyright | (c) 2018-2019 Yann Herklotz |
---|---|
License | BSD-3 |
Maintainer | yann [at] yannherklotz [dot] com |
Stability | experimental |
Portability | POSIX |
Safe Haskell | None |
Language | Haskell2010 |
Defaults and common functions.
Synopsis
- regDecl :: Identifier -> ModItem
- wireDecl :: Identifier -> ModItem
- emptyMod :: ModDecl
- setModName :: Text -> ModDecl -> ModDecl
- addModPort :: Port -> ModDecl -> ModDecl
- addModDecl :: ModDecl -> Verilog -> Verilog
- testBench :: ModDecl
- addTestBench :: Verilog -> Verilog
- defaultPort :: Identifier -> Port
- portToExpr :: Port -> Expr
- modName :: ModDecl -> Text
- yPort :: Identifier -> Port
- wire :: Range -> Identifier -> Port
- reg :: Range -> Identifier -> Port
Documentation
regDecl :: Identifier -> ModItem Source #
wireDecl :: Identifier -> ModItem Source #
addTestBench :: Verilog -> Verilog Source #
defaultPort :: Identifier -> Port Source #
portToExpr :: Port -> Expr Source #
yPort :: Identifier -> Port Source #