# Mustache template for Intel Quartus projects
# for more details see: Quartus II Handbook Version 11.0 Volume 2
# and Quartus II Scripting Reference Manual

set myScript "{{project}}.tcl"

# Load Quartus Prime Tcl Project packages
package require ::quartus::project

# Add the next line to get the execute_flow command
package require ::quartus::flow

set need_to_close_project 0
set make_assignments 1

# This procedure will open a quartus project
proc Open {prj_name} {
    global need_to_close_project
    # Check that the right project is open
    if {[is_project_open]} {
        if {[string compare $quartus(project) $prj_name]} {
            puts "Project is not open"
            set make_assignments 0
        }
    } else {
        # Only open if not already open
        if {[project_exists $prj_name]} {
            set current_revision [get_current_revision $prj_name]
                project_open -revision $current_revision $prj_name
        } else {
            project_new -revision $prj_name $prj_name
        }
        set need_to_close_project 1
    }
}

# This procedure adds files to quartus .qsf file
proc Addfile {src_file {library "lib"} } {
    if [regexp {.vhdl?$} $src_file] {
        set_global_assignment -name VHDL_FILE "$src_file" -library "$library"
    } elseif [regexp {.sv?$} $src_file] {
        set_global_assignment -name SYSTEMVERILOG_FILE "$src_file" -library "$library"
    } elseif [regexp {.v?$} $src_file] {
        set_global_assignment -name VERILOG_FILE "$src_file" -library "$library"
    } else {
        puts "Unknown file type: $src_file"
    }
    # Commit assignments
    export_assignments
}

# Open project
Open "{{project}}"

# Make assignments
if {$make_assignments} {
    set_global_assignment -name FAMILY "{{targetFamily}}"
    set_global_assignment -name DEVICE "{{targetDevice}}"
    set_global_assignment -name PROJECT_OUTPUT_DIRECTORY "./"
    set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
    set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
    set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR ./netlist -section_id eda_simulation
    set_global_assignment -name EDA_OUTPUT_DATA_FORMAT Verilog -section_id eda_simulation
    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

    # Setup top entity
    set_global_assignment -name TOP_LEVEL_ENTITY "{{top}}"

    # Source settings
    {{#tclSrcs}}
    source "{{fileName}}"
    {{/tclSrcs}}

    # Source constrains
    {{#constraintSrcs}}
    set_global_assignment -name SDC_FILE "{{fileName}}"
    {{/constraintSrcs}}

    puts "$myScript: Adding sources to project..."

    # Add QIP files (from ip dir)
    {{#ipcores}}
    set_global_assignment -name QIP_FILE "{{fileName}}"
    {{/ipcores}}

    # Add sources to the project
    {{#srcs}}
    Addfile "{{fileName}}"
    {{/srcs}}

    # Commit assignments
    export_assignments
}

execute_flow -compile

# Close project
if {$need_to_close_project} {
    puts "Closing project"
    project_close
}