Copyright	(C) 2015-2016 University of Twente 2017 Google Inc. 2019 Myrtle Software Ltd 2021-2022 QBayLogic B.V.
License	BSD2 (see the file LICENSE)
Maintainer	QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell	Trustworthy
Language	Haskell2010
Extensions	Cpp MonoLocalBinds ScopedTypeVariables BangPatterns TypeFamilies ViewPatterns DataKinds InstanceSigs StandaloneDeriving DeriveDataTypeable DeriveFunctor DeriveTraversable DeriveFoldable DeriveGeneric DefaultSignatures DeriveLift DerivingStrategies FlexibleContexts MagicHash KindSignatures PostfixOperators TupleSections TypeOperators ExplicitNamespaces ExplicitForAll BinaryLiterals TypeApplications

Clash.Explicit.RAM

Contents

Description

RAM primitives with a combinational read port.

Synopsis

asyncRam :: (Enum addr, NFDataX addr, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom addr -> Signal wdom (Maybe (addr, a)) -> Signal rdom a
asyncRamPow2 :: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> Signal rdom (Unsigned n) -> Signal wdom (Maybe (Unsigned n, a)) -> Signal rdom a
asyncRam# :: forall wdom rdom n a. (HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom Int -> Signal wdom Bool -> Signal wdom Int -> Signal wdom a -> Signal rdom a

RAM synchronized to an arbitrary clock

Arguments

:: (Enum addr, NFDataX addr, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a)
=> Clock wdom	`Clock` to which the write port of the RAM is synchronized
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom	`Enable` line for the write port
-> SNat n	Size `n` of the RAM
-> Signal rdom addr	Read address `r`
-> Signal wdom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the RAM at address `r`

Create a RAM with space for n elements

NB: Initial content of the RAM is undefined, reading it will throw an XException

Internal

Arguments

:: forall wdom rdom n a. (HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a)
=> Clock wdom	`Clock` to which the write port of the RAM is synchronized
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom	`Enable` line for the write port
-> SNat n	Size `n` of the RAM
-> Signal rdom Int	Read address `r`
-> Signal wdom Bool	Write enable
-> Signal wdom Int	Write address `w`
-> Signal wdom a	Value to write (at address `w`)
-> Signal rdom a	Value of the RAM at address `r`

RAM primitive

:: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom, NFDataX a)
=> Clock wdom	`Clock` to which the write port of the RAM is synchronized
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom	`Enable` line for the write port
-> Signal rdom (Unsigned n)	Read address `r`
-> Signal wdom (Maybe (Unsigned n, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the RAM at address `r`