Copyright	(C) 2015-2016 University of Twente 2017 Google Inc. 2019 Myrtle Software Ltd
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	Trustworthy
Language	Haskell2010
Extensions	Cpp MonoLocalBinds ScopedTypeVariables BangPatterns TypeFamilies ViewPatterns DataKinds InstanceSigs StandaloneDeriving DeriveDataTypeable DeriveFunctor DeriveTraversable DeriveFoldable DeriveGeneric DefaultSignatures DeriveLift DerivingStrategies FlexibleContexts MagicHash KindSignatures TupleSections TypeOperators ExplicitNamespaces ExplicitForAll BinaryLiterals TypeApplications

Clash.Explicit.RAM

Contents

Description

RAM primitives with a combinational read port.

Synopsis

asyncRam :: (Enum addr, HasCallStack, KnownDomain wdom, KnownDomain rdom) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom addr -> Signal wdom (Maybe (addr, a)) -> Signal rdom a
asyncRamPow2 :: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom) => Clock wdom -> Clock rdom -> Enable wdom -> Signal rdom (Unsigned n) -> Signal wdom (Maybe (Unsigned n, a)) -> Signal rdom a
asyncRam# :: (HasCallStack, KnownDomain wdom, KnownDomain rdom) => Clock wdom -> Clock rdom -> Enable wdom -> SNat n -> Signal rdom Int -> Signal wdom Bool -> Signal wdom Int -> Signal wdom a -> Signal rdom a

RAM synchronized to an arbitrary clock

Arguments

:: (Enum addr, HasCallStack, KnownDomain wdom, KnownDomain rdom)
=> Clock wdom	`Clock` to which to synchronize the write port of the RAM
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized to
-> Enable wdom	Global enable
-> SNat n	Size `n` of the RAM
-> Signal rdom addr	Read address `r`
-> Signal wdom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for n elements

Additional helpful information:

Arguments

:: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom)
=> Clock wdom	`Clock` to which to synchronize the write port of the RAM
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom	Global enable
-> Signal rdom (Unsigned n)	Read address `r`
-> Signal wdom (Maybe (Unsigned n, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for 2^n elements

Additional helpful information:

Internal

Arguments

:: (HasCallStack, KnownDomain wdom, KnownDomain rdom)
=> Clock wdom	`Clock` to which to synchronize the write port of the RAM
-> Clock rdom	`Clock` to which the read address signal, `r`, is synchronized
-> Enable wdom	Global enable
-> SNat n	Size `n` of the RAM
-> Signal rdom Int	Read address `r`
-> Signal wdom Bool	Write enable
-> Signal wdom Int	Write address `w`
-> Signal wdom a	Value to write (at address `w`)
-> Signal rdom a	Value of the `RAM` at address `r`

RAM primitive