clash-prelude-1.2.0: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2017 Google Inc
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellNone
LanguageHaskell2010

Clash.Xilinx.DDR

Description

DDR primitives for Xilinx FPGAs

For general information about DDR primitives see Clash.Explicit.DDR.

For more information about the Xilinx DDR primitives see:

Synopsis

Documentation

iddr Source #

Arguments

:: (HasCallStack, KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) 
=> Clock slow

clock

-> Reset slow

reset

-> Enable slow

global enable

-> Signal fast (BitVector m)

DDR input signal

-> Signal slow (BitVector m, BitVector m)

normal speed output pairs

Xilinx specific variant of ddrIn implemented using the Xilinx IDDR primitive in SAME_EDGE mode.

Reset values are 0

oddr Source #

Arguments

:: (KnownConfiguration fast (DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow (DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) 
=> Clock slow

clock

-> Reset slow

reset

-> Enable slow

global enable

-> Signal slow (BitVector m, BitVector m)

normal speed input pairs

-> Signal fast (BitVector m)

DDR output signal

Xilinx specific variant of ddrOut implemented using the Xilinx ODDR primitive in SAME_EDGE mode.

Reset value is 0