| Copyright | (C) 2015-2016 University of Twente 2017 Google Inc. |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | Safe |
| Language | Haskell2010 |
| Extensions |
|
Clash.Explicit.ROM
Description
ROMs
Synopsis
- rom :: (KnownNat n, Enum addr) => Clock domain gated -> Vec n a -> Signal domain addr -> Signal domain a
- romPow2 :: KnownNat n => Clock domain gated -> Vec (2 ^ n) a -> Signal domain (Unsigned n) -> Signal domain a
- rom# :: KnownNat n => Clock domain gated -> Vec n a -> Signal domain Int -> Signal domain a
Synchronous ROM synchronised to an arbitrary clock
Arguments
| :: (KnownNat n, Enum addr) | |
| => Clock domain gated |
|
| -> Vec n a | ROM content NB: must be a constant |
| -> Signal domain addr | Read address |
| -> Signal domain a | The value of the ROM at address |
A ROM with a synchronous read port, with space for n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
Additional helpful information:
- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs
Arguments
| :: KnownNat n | |
| => Clock domain gated |
|
| -> Vec (2 ^ n) a | ROM content NB: must be a constant |
| -> Signal domain (Unsigned n) | Read address |
| -> Signal domain a | The value of the ROM at address |
A ROM with a synchronous read port, with space for 2^n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
Additional helpful information:
- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs