| Copyright | (C) 2015-2016 University of Twente 2017 Myrtle Software Ltd Google Inc. |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | Safe |
| Language | Haskell2010 |
| Extensions |
|
Clash.Prelude.RAM
Description
RAM primitives with a combinational read port.
Synopsis
- asyncRam :: (Enum addr, HiddenClock domain gated, HasCallStack) => SNat n -> Signal domain addr -> Signal domain (Maybe (addr, a)) -> Signal domain a
- asyncRamPow2 :: (KnownNat n, HiddenClock domain gated, HasCallStack) => Signal domain (Unsigned n) -> Signal domain (Maybe (Unsigned n, a)) -> Signal domain a
RAM synchronised to an arbitrary clock
Arguments
| :: (Enum addr, HiddenClock domain gated, HasCallStack) | |
| => SNat n | Size |
| -> Signal domain addr | Read address |
| -> Signal domain (Maybe (addr, a)) | (write address |
| -> Signal domain a | Value of the |
Create a RAM with space for n elements.
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See Clash.Prelude.BlockRam for more information on how to use a RAM.
Arguments
| :: (KnownNat n, HiddenClock domain gated, HasCallStack) | |
| => Signal domain (Unsigned n) | Read address |
| -> Signal domain (Maybe (Unsigned n, a)) | (write address |
| -> Signal domain a | Value of the |
Create a RAM with space for 2^n elements
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See Clash.Prelude.BlockRam for more information on how to use a RAM.