- BlackBox: name: Clash.Explicit.RAM.asyncRam# kind: Declaration type: |- asyncRam# :: ( HasCallStack -- ARG[0] , KnownDomain wdom -- ARG[1] , KnownDomain rdom -- ARG[2] , NFDataX a ) -- ARG[3] => Clock wdom -- ^ wclk, ARG[4] -> Clock rdom -- ^ rclk, ARG[5] -> Enable wdom -- ^ wen, ARG[6] -> SNat n -- ^ sz, ARG[7] -> Signal rdom Int -- ^ rd, ARG[8] -> Signal wdom Bool -- ^ en, ARG[9] -> Signal wdom Int -- ^ wr, ARG[10] -> Signal wdom a -- ^ din, ARG[11] -> Signal rdom a template: |- -- asyncRam begin ~GENSYM[~COMPNAME_asyncRam][0] : block~IF ~VIVADO ~THEN type ~GENSYM[RamType][4] is array(natural range <>) of std_logic_vector(~SIZE[~TYP[11]]-1 downto 0);~ELSE type ~SYM[4] is array(natural range <>) of ~TYP[11];~FI signal ~GENSYM[RAM][1] : ~SYM[4](0 to ~LIT[7]-1); signal ~GENSYM[rd][2] : integer range 0 to ~LIT[7] - 1; signal ~GENSYM[wr][3] : integer range 0 to ~LIT[7] - 1; begin ~SYM[2] <= to_integer(~VAR[rdI][8](31 downto 0)) -- pragma translate_off mod ~LIT[7] -- pragma translate_on ; ~SYM[3] <= to_integer(~VAR[wrI][10](31 downto 0)) -- pragma translate_off mod ~LIT[7] -- pragma translate_on ; ~GENSYM[asyncRam_sync][7] : process(~ARG[4]) begin if ~IF~ACTIVEEDGE[Rising][1]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then if (~ARG[9] ~IF ~ISACTIVEENABLE[6] ~THEN and ~ARG[6] ~ELSE ~FI) then~IF ~VIVADO ~THEN ~SYM[1](~SYM[3]) <= ~TOBV[~ARG[11]][~TYP[11]];~ELSE ~SYM[1](~SYM[3]) <= ~ARG[11];~FI end if; end if; end process; ~IF ~VIVADO ~THEN ~RESULT <= ~FROMBV[~SYM[1](~SYM[2])][~TYP[11]];~ELSE ~RESULT <= ~SYM[1](~SYM[2]);~FI end block; -- asyncRam end