- BlackBox:
    name: Clash.Explicit.BlockRam.File.blockRamFile#
    kind: Declaration
    type: |-
      blockRamFile#
        :: ( KnownDomain dom        -- ARG[0]
           , KnownNat m             -- ARG[1]
           , HasCallStack )         -- ARG[2]
        => Clock dom                -- clk,  ARG[3]
        => Enable dom               -- en,   ARG[4]
        -> SNat n                   -- sz,   ARG[5]
        -> FilePath                 -- file, ARG[6]
        -> Signal dom Int           -- rd,   ARG[7]
        -> Signal dom Bool          -- wren, ARG[8]
        -> Signal dom Int           -- wr,   ARG[9]
        -> Signal dom (BitVector m) -- din,  ARG[10]
        -> Signal dom (BitVector m)
    template: |-
      -- blockRamFile begin
      ~GENSYM[~COMPNAME_blockRamFile][1] : block
        type ~GENSYM[RamType][7] is array(natural range <>) of bit_vector(~LIT[1]-1 downto 0);

        impure function ~GENSYM[InitRamFromFile][2] (RamFileName : in string) return ~SYM[7] is
          FILE RamFile : text open read_mode is RamFileName;
          variable RamFileLine : line;
          variable RAM : ~SYM[7](0 to ~LIT[5]-1);
        begin
          for i in RAM'range loop
            readline(RamFile,RamFileLine);
            read(RamFileLine,RAM(i));
          end loop;
          return RAM;
        end function;

        signal ~GENSYM[RAM][3] : ~SYM[7](0 to ~LIT[5]-1) := ~SYM[2](~FILE[~LIT[6]]);
        signal ~GENSYM[rd][5]  : integer range 0 to ~LIT[5]-1;
        signal ~GENSYM[wr][6]  : integer range 0 to ~LIT[5]-1;
      begin
        ~SYM[5] <= to_integer(~VAR[rdI][7](31 downto 0))
        -- pragma translate_off
                      mod ~LIT[5]
        -- pragma translate_on
                      ;

        ~SYM[6] <= to_integer(~VAR[wrI][9](31 downto 0))
        -- pragma translate_off
                      mod ~LIT[5]
        -- pragma translate_on
                      ;
        ~IF ~VIVADO ~THEN ~IF ~ISACTIVEENABLE[4] ~THEN
        ~GENSYM[blockRamFile_sync][10] : process(~ARG[3])
        begin
          if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
            if ~ARG[4] then
              if ~ARG[8] then
                ~SYM[3](~SYM[6]) <= to_bitvector(~ARG[10]);
              end if;
              ~RESULT <= to_stdlogicvector(~SYM[3](~SYM[5]));
            end if;
          end if;
        end process;~ELSE
        ~SYM[10] : process(~ARG[3])
        begin
          if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
            if ~ARG[8] then
              ~SYM[3](~SYM[6]) <= to_bitvector(~ARG[10]);
            end if;
            ~RESULT <= to_stdlogicvector(~SYM[3](~SYM[5]));
          end if;
        end process;~FI ~ELSE ~IF ~ISACTIVEENABLE[4] ~THEN
        ~SYM[10] : process(~ARG[3])
        begin
          if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
            if ~ARG[8] and ~ARG[4] then
              ~SYM[3](~SYM[6]) <= to_bitvector(~ARG[10]);
            end if;
            if ~ARG[4] then
              ~RESULT <= to_stdlogicvector(~SYM[3](~SYM[5]));
            end if;
          end if;
        end process;~ELSE
        ~SYM[10] : process(~ARG[3])
        begin
          if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
            if ~ARG[8] then
              ~SYM[3](~SYM[6]) <= to_bitvector(~ARG[10]);
            end if;
            ~RESULT <= to_stdlogicvector(~SYM[3](~SYM[5]));
          end if;
        end process;~FI ~FI
      end block;
      -- blockRamFile end