Throw away information indicating which constructor fields were filtered due to being void.

Determines if type is a zero-width construct ("void")

Same as isVoid, but on FilteredHWType instead of HWType

Split a normalized term into: a list of arguments, a list of let-bindings, and a variable reference that is the body of the let-binding. Returns a String containing the error if the term was not in a normalized form.

Same as unsafeCoreTypeToHWType, but discards void filter information

Converts a Core type to a HWType given a function that translates certain builtin types. Errors if the Core type is not translatable.

Same as unsafeCoreTypeToHWTypeM, but discards void filter information

Converts a Core type to a HWType within the NetlistMonad; errors on failure

Same as coreTypeToHWTypeM, but discards void filter information

Converts a Core type to a HWType within the NetlistMonad; Nothing on failure

Same as coreTypeToHWType, but discards void filter information

Converts a Core type to a HWType given a function that translates certain builtin types. Returns a string containing the error message when the Core type is not translatable.

Generates original indices in list before filtering, given a list of removed indices.

>>> originalIndices [False, False, True, False]
[0,1,3]

Converts an algebraic Core type (split into a TyCon and its argument) to a HWType.

Simple check if a TyCon is recursively defined.

Determines if a Core type is translatable to a HWType given a function that translates certain builtin types.

Determines the bitsize of a type. For types that don't get turned into real values in hardware (string, integer) the size is 0.

Determines the bitsize of the constructor of a type

Gives the length of length-indexed types

Gives the HWType corresponding to a term. Returns an error if the term has a Core type that is not translatable to a HWType.

Gives the HWType corresponding to a term. Returns Nothing if the term has a Core type that is not translatable to a HWType.

Helper function of collectPortNames, which operates on a PortName instead of a TopEntity.

Recursively get all port names from top entity annotations. The result is a list of user defined port names, which should not be used by routines generating unique function names. Only completely qualified names are returned, as it does not (and cannot) account for any implicitly named ports under a PortProduct.

Remove ports having a void-type from user supplied PortName annotation

Uniquely rename all the variables and their references in a normalized term

Same as idToPort, but * Throws an error if the port is a composite type with a BiSignalIn

Same as idToPort, but: * Throws an error if port is of type BiSignalIn

Make a set of IDs unique; also returns a substitution from old ID to new updated unique ID.

Preserve the Netlist _varCount,_curCompNm,_seenIds when executing a monadic action

Prefix given string before portnames except when this string is empty.

In addition to the original port name (where the user should assert that it's a valid identifier), we also add the version of the port name that has gone through the 'mkIdentifier Basic' process. Why? so that the provided port name is copied verbatim into the generated HDL, but that in e.g. case-insensitive HDLs, a case-variant of the port name is not used as one of the signal names.

Create a Vector chain for a list of Identifiers

Create a RTree chain for a list of Identifiers

Strips one or more layers of attributes from a HWType; stops at first non-Annotated. Accumilates all attributes of nested annotations.

Generate output port mappings

Generate output port mappings. Will yield Nothing if the only output is Void.

Instantiate a TopEntity, and add the proper type-conversions where needed

Convert between BitVector for an argument

Convert between BitVector for the result

Add to/from-BitVector conversion logic

Generate input port mappings for the TopEntity

Consider the following type signature:

  f :: Signal dom (Vec 6 A) `Annotate` Attr "keep"
    -> Signal dom (Vec 6 B)

What does the annotation mean, considering that Clash will split these vectors into multiple in- and output ports? Should we apply the annotation to all individual ports? How would we handle pin mappings? For now, we simply throw an error. This is a helper function to do so.

Generate output port mappings for the TopEntity. Yields Nothing if the output is Void

Generate output port mappings for the TopEntity

Try to merge nested modifiers into a single modifier, needed by the VHDL and SystemVerilog backend.

Determines if any type variables (exts) are bound in any of the given type or term variables (tms). It's currently only used to detect bound existentials, hence the name.

Run a NetlistMonad computation in the context of the given source ticks and name modifier ticks

Add the pre- and suffix names in the current environment to the given identifier