Safe Haskell | None |
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Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs
Documentation
:: DebugLevel | |
-> Supply | |
-> PrimMap | Primitives |
-> (Type -> Maybe (Either String HWType)) | |
-> VHDLState | |
-> HashMap TmName (Type, Term) | Global binders |
-> Maybe TmName | Stimuli |
-> Maybe TmName | Expected output |
-> Component | Component to generate TB for |
-> IO ([Component], VHDLState) |
Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs