clash-lib-0.2.0.1: CAES Language for Synchronous Hardware - As a Library

Safe HaskellNone

CLaSH.Driver.TestbenchGen

Description

Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs

Synopsis

Documentation

genTestBenchSource

Arguments

:: DebugLevel 
-> Supply 
-> PrimMap

Primitives

-> (Type -> Maybe (Either String HWType)) 
-> VHDLState 
-> HashMap TmName (Type, Term)

Global binders

-> Maybe TmName

Stimuli

-> Maybe TmName

Expected output

-> Component

Component to generate TB for

-> IO ([Component], VHDLState) 

Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs