clash-ghc: CAES Language for Synchronous Hardware

[ bsd2, hardware, library, program ] [ Propose Tags ]

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, which enables both safe and fast prototying using consise descriptions (like Verilog)

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals.

  • Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

  • CλaSH Compiler binary using GHC/Haskell as a frontend

Prelude library: http://hackage.haskell.org/package/clash-prelude


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Note: This package has metadata revisions in the cabal description newer than included in the tarball. To unpack the package including the revisions, use 'cabal get'.

Versions [RSS] 0.2.1, 0.2.2, 0.2.2.1, 0.2.2.2, 0.3, 0.3.0.1, 0.3.0.2, 0.3.0.3, 0.3.1, 0.3.2, 0.3.3, 0.4, 0.4.1, 0.5, 0.5.1, 0.5.2, 0.5.3, 0.5.4, 0.5.5, 0.5.6, 0.5.7, 0.5.8, 0.5.9, 0.5.10, 0.5.11, 0.5.12, 0.5.13, 0.5.14, 0.5.15, 0.6, 0.6.1, 0.6.2, 0.6.3, 0.6.4, 0.6.5, 0.6.6, 0.6.7, 0.6.8, 0.6.9, 0.6.10, 0.6.11, 0.6.12, 0.6.13, 0.6.14, 0.6.15, 0.6.16, 0.6.17, 0.6.18, 0.6.19, 0.6.20, 0.6.21, 0.6.22, 0.6.23, 0.6.24, 0.7, 0.7.0.1, 0.7.1, 0.7.2, 0.99, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1, 1.2.0, 1.2.1, 1.2.2, 1.2.3, 1.2.4, 1.2.5, 1.4.0, 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5, 1.4.6, 1.4.7, 1.6.0, 1.6.1, 1.6.2, 1.6.3, 1.6.4, 1.6.5, 1.6.6, 1.8.0, 1.8.1 (info)
Change log CHANGELOG.md
Dependencies array (>=0.4), base (>=4.3.1.0 && <5), bifunctors (>=4.1.1), bytestring (>=0.9), clash-lib (>=0.5.11 && <0.6), clash-prelude (>=0.9.2 && <0.10), clash-systemverilog (>=0.5.8), clash-verilog (>=0.5.8), clash-vhdl (>=0.5.9), containers (>=0.5.4.0), directory (>=1.2), filepath (>=1.3), ghc (>=7.10.1 && <7.12), ghc-typelits-natnormalise (>=0.3), hashable (>=1.1.2.3), haskeline (>=0.7.0.3), lens (>=4.0.5), mtl (>=2.1.1), process (>=1.2), text (>=0.11.3.1), transformers (>=0.4.2), unbound-generics (>=0.1 && <0.3), unix, unordered-containers (>=0.2.1.0), Win32 [details]
License BSD-2-Clause
Copyright Copyright © 2012-2015 University of Twente
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Revised Revision 1 made by ChristiaanBaaij at 2015-10-20T09:18:56Z
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repo head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded by ChristiaanBaaij at 2015-09-07T12:31:51Z
Distributions Arch:1.8.0, Stackage:1.8.1
Reverse Dependencies 5 direct, 0 indirect [details]
Executables clash
Downloads 67521 total (275 in the last 30 days)
Rating 2.25 (votes: 2) [estimated by Bayesian average]
Your Rating
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Status Docs not available [build log]
All reported builds failed as of 2016-11-30 [all 6 reports]

Readme for clash-ghc-0.5.12

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clash-ghc - Haskell/GHC front-end for the CλaSH compiler

  • See the LICENSE file for license and copyright details
  • Contains code from the GHC compiler, see the LICENSE_GHC file for license and copyright details pertaining to that code.

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, which enables both safe and fast prototying using consise descriptions (like Verilog)

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum