{-# LANGUAGE QuasiQuotes #-}
module Verismith.Verilog
( SourceInfo(..)
, Verilog(..)
, parseVerilog
, GenVerilog(..)
, genSource
, Identifier(..)
, Delay(..)
, Event(..)
, BinaryOperator(..)
, UnaryOperator(..)
, Task(..)
, taskName
, taskExpr
, LVal(..)
, regId
, regExprId
, regExpr
, regSizeId
, regSizeRange
, regConc
, PortDir(..)
, PortType(..)
, Port(..)
, portType
, portSigned
, portSize
, portName
, Expr(..)
, ConstExpr(..)
, constToExpr
, exprToConst
, constNum
, Assign(..)
, assignReg
, assignDelay
, assignExpr
, ContAssign(..)
, contAssignNetLVal
, contAssignExpr
, Statement(..)
, statDelay
, statDStat
, statEvent
, statEStat
, statements
, stmntBA
, stmntNBA
, stmntTask
, stmntSysTask
, stmntCondExpr
, stmntCondTrue
, stmntCondFalse
, ModDecl(..)
, modId
, modOutPorts
, modInPorts
, modItems
, ModItem(..)
, modContAssign
, modInstId
, modInstName
, modInstConns
, traverseModItem
, declDir
, declPort
, ModConn(..)
, modConnName
, modExpr
, getModule
, getSourceId
, verilog
)
where
import Verismith.Verilog.AST
import Verismith.Verilog.CodeGen
import Verismith.Verilog.Parser
import Verismith.Verilog.Quote