kansas-lava-papilio-0.3.1: Kansas Lava support files for the Papilio FPGA board

Safe HaskellNone
LanguageHaskell2010

Language.KansasLava.Signal.Utils

Documentation

splitByte :: (sig ~ Signal c) => sig (Unsigned X8) -> (sig (Unsigned X4), sig (Unsigned X4)) Source

debounce :: forall c sig n. (Clock c, sig ~ Signal c, Size n) => Witness n -> sig Bool -> (sig Bool, sig Bool, sig Bool) Source

nary :: forall a clk sig n. (Clock clk, sig ~ Signal clk, Rep a, Size n, Rep n) => sig n -> Matrix n (sig a) -> sig a Source

divideClk :: forall c sig ix. (Clock c, sig ~ Signal c, Size ix) => Witness ix -> sig Bool Source

counter :: (Rep a, Num a, Bounded a, Eq a, Clock c, sig ~ Signal c) => sig Bool -> sig a Source

rotatorL :: (Clock c, sig ~ Signal c, Size ix, Integral ix) => sig Bool -> Matrix ix (sig Bool) Source

fromUnsigned :: (sig ~ Signal c, Size ix) => sig (Unsigned ix) -> Matrix ix (sig Bool) Source

toUnsigned :: (sig ~ Signal c, Size ix) => Matrix ix (sig Bool) -> sig (Unsigned ix) Source

parity :: forall clk n. (Clock clk, Size n, Rep n, Integral n, Enum n) => Signal clk (Unsigned n) -> Signal clk Bool Source

whenEnabled :: (Clock clk, Rep a) => Signal clk (Enabled a) -> (Signal clk a -> RTL s clk ()) -> RTL s clk () Source