Safe Haskell | None |
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Language | Haskell2010 |
Documentation
:: Ident | Name of the instantiated DCM module |
-> Ident |
|
-> Ident |
|
-> Module | Module using |
-> Module |
Interface to the Xilinx Digital Clock Manager module.
The DCM definition itself must be created separately in the Xilinx ISE as a
.xaw
file.
The following example creates a circuit running at 16 MHz with a native clock signal of 32 MHz.
kleg <- reifyFabric $ do theClk "CLK_16MHZ" fabric mod <- netlistCircuit modName kleg let mod' = dcm "dcm_32_to_16" "CLK_32MHZ" "CLK_16MHZ" mod vhdl = genVHDL mod' ["work.lava.all", "work.all"] return vhdl