ice40-prim: Lattice iCE40 Primitive IP

[ bsd3, hardware, library ] [ Propose Tags ]

Clash primitives to instantiate Lattice Semiconductor's iCE40 FPGA hard IP


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Versions [RSS] [faq] 0.1.0.0, 0.2.0.0, 0.3.0.0, 0.3.0.1, 0.3.1.0, 0.3.1.1
Change log CHANGELOG.md
Dependencies base (>=4.12 && <4.16), clash-prelude (>=1.2.5 && <1.5), ghc-typelits-extra, ghc-typelits-knownnat, ghc-typelits-natnormalise, interpolate (==0.2.*) [details]
License BSD-3-Clause
Copyright Copyright (c) 2020-2021 David Cox
Author dopamane
Maintainer dopamane <standard.semiconductor@gmail.com>
Category Hardware
Bug tracker https://github.com/standardsemiconductor/ice40-prim/issues
Source repo head: git clone https://github.com/standardsemiconductor/ice40-prim
Uploaded by dopamane at 2021-07-02T02:17:54Z
Distributions NixOS:0.3.1.1
Downloads 1138 total (119 in the last 30 days)
Rating 2.0 (votes: 1) [estimated by Bayesian average]
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Status Hackage Matrix CI
Docs available [build log]
Last success reported on 2021-07-02 [all 1 reports]

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Readme for ice40-prim-0.3.1.1

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ice40-prim

Haskell CI Hackage Hackage Dependencies

Lattice iCE40 Primitive IP

Supported IP Modules

  • Ice40.Spram - For more information see the iCE40 SPRAM Usage Guide

    • sysMem Single Port RAM Memory (SPRAM)
    • Each block of SPRAM is 16k x 16 (256 kbits)
    • 16-bit data width with nibble mast control
    • Cascadable design for deeper/wider SPRAM
    • Three power modes, standby, sleep, and power off
  • Ice40.Mac - For more information see the DSP Function Usage Guide PDF

    • 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit multipliers
    • Optional independent pipeline control on input Register, Output Register, and Intermediate Register for faster clock performance
    • 32-bit accumulator, or two independent 16-bit accumulators
    • 32-bit, or two independent 16-bit adder/subtractor functions, registered or asynchronous
    • Cascadable to create wider accumulator blocks
  • Ice40.Osc - For more information see the iCE40 Oscillator Usage Guide

    • on-chip oscillator
    • Low-power low frequency oscillator of 10 kHz
    • High frequency oscillator configurable to 48 Mhz, 24 Mhz, 12 Mhz, or 6 Mhz
    • See also Ice40.Clock for clock domains and reset
  • Ice40.Pll - For more information see the iCE40 sysCLOCK PLL Design and Usage Guide

    • Pad and Core variants
    • Phase Lock Loop (PLL)
    • Provides a variety of user-synthesizable clock frequencies along with custom phase delays
    • Generates a new output clock freuquency via clock multiplication and division
    • De-skews or phase-aligns an output clock to the input reference clock
    • Corrects output clock to have nearly a 50% duty cycle, which is important for Double Data Rate (DDR) applications
  • Ice40.Rgb - For more information see the iCE40 LED Driver Usage Guide

    • RGB High Current Drive I/O Pins
    • Provides sinking current to an LED connecting to the positive supply
    • Three outputs designed to drive the RGB LEDs
    • RGB drive current is user programmable from 4mA to 24mA, in increments of 4mA
  • Ice40.Led - For more information see the iCE40 LED Driver Usage Guide PDF

    • LED PWM IP
    • Provide easier usage of RGB high current drivers
    • Provides flexibility for user to dynamically change the modulation width of each of the RGB LED driver
    • User can dynamically change ON and OFF-time durations
    • Ability to turn LEDs on and off gradually with breath-on and breath-off time
  • Ice40.Spi - For more information see the Advanced SPI and I2C Usage Guide PDF

    • User SPI IP
    • Configurable Boss and Worker modes
    • Full-Duplex data transfer
    • Mode fault error flag with CPU interrupt capability
    • Double-buffered data register
    • Serial clock with programmable polarity and phase
    • LSB First or MSB First data transfer
  • Ice40.IO

    • IO primitive
  • Ice40.GB

    • Global buffer primitive
    • Required for a user's internally generated FPGA signal that is heavily loaded and requires global buffering; for example, a user's logic-generated clock
  • Ice40.I2c - For more information see the Advanced SPI and I2C Usage Guide PDF

    • User I2C IP
    • Boss and Worker operation
    • 7-bit and 10-bit addressing
    • Multi-master arbitration support
    • Clock stretching
    • Up to 400 kHz data transfer speed
    • General Call support
    • Optionally delaying input or output data, or both
    • Optional filter on SCL input

Lattice Documentation

iCE40 UltraPlus Family Data Sheet PDF

iCE Technology Library PDF

Advanced SPI and I2C Usage Guide PDF

iCE40 LED Driver Usage Guide PDF

iCE40 SPRAM Usage Guide

DSP Function Usage Guide PDF

iCE40 sysCLOCK PLL Design and Usage Guide