Copyright	(C) 2015-2016 University of Twente 2017-2019 Myrtle Software Ltd 2017 Google Inc. 2021-2022 QBayLogic B.V.
License	BSD2 (see the file LICENSE)
Maintainer	QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell	Safe
Language	Haskell2010
Extensions	Cpp MonoLocalBinds ScopedTypeVariables BangPatterns TypeFamilies ViewPatterns DataKinds InstanceSigs StandaloneDeriving DeriveDataTypeable DeriveFunctor DeriveTraversable DeriveFoldable DeriveGeneric DefaultSignatures DeriveLift DerivingStrategies FlexibleContexts MagicHash KindSignatures TupleSections TypeOperators ExplicitNamespaces ExplicitForAll BinaryLiterals TypeApplications

Clash.Prelude.RAM

Contents

Description

RAM primitives with a combinational read port

Synopsis

RAM synchronized to an arbitrary clock

Arguments

:: (Enum addr, HiddenClock dom, HiddenEnable dom, HasCallStack, NFDataX a)
=> SNat n	Size `n` of the RAM
-> Signal dom addr	Read address `r`
-> Signal dom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal dom a	Value of the RAM at address `r`

Create a RAM with space for n elements

NB: Initial content of the RAM is undefined, reading it will throw an XException

:: (KnownNat n, HiddenClock dom, HiddenEnable dom, HasCallStack, NFDataX a)
=> Signal dom (Unsigned n)	Read address `r`
-> Signal dom (Maybe (Unsigned n, a))	(write address `w`, value to write)
-> Signal dom a	Value of the RAM at address `r`