| Copyright | (C) 2015-2016 University of Twente 2017 Google Inc. 2019 Myrtle Software Ltd |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | Trustworthy |
| Language | Haskell2010 |
| Extensions |
|
Clash.Explicit.ROM
Description
ROMs
Synopsis
- rom :: (KnownDomain dom, KnownNat n, Undefined a, Enum addr) => Clock dom -> Enable dom -> Vec n a -> Signal dom addr -> Signal dom a
- romPow2 :: (KnownDomain dom, KnownNat n, Undefined a) => Clock dom -> Enable dom -> Vec (2 ^ n) a -> Signal dom (Unsigned n) -> Signal dom a
- rom# :: forall dom n a. (KnownDomain dom, KnownNat n, Undefined a) => Clock dom -> Enable dom -> Vec n a -> Signal dom Int -> Signal dom a
Synchronous ROM synchronized to an arbitrary clock
Arguments
| :: (KnownDomain dom, KnownNat n, Undefined a, Enum addr) | |
| => Clock dom |
|
| -> Enable dom | Global enable |
| -> Vec n a | ROM content NB: must be a constant |
| -> Signal dom addr | Read address |
| -> Signal dom a | The value of the ROM at address |
A ROM with a synchronous read port, with space for n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
Additional helpful information:
- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs
Arguments
| :: (KnownDomain dom, KnownNat n, Undefined a) | |
| => Clock dom |
|
| -> Enable dom | Global enable |
| -> Vec (2 ^ n) a | ROM content NB: must be a constant |
| -> Signal dom (Unsigned n) | Read address |
| -> Signal dom a | The value of the ROM at address |
A ROM with a synchronous read port, with space for 2^n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
Additional helpful information:
- See Clash.Sized.Fixed and Clash.Explicit.BlockRam for ideas on how to use ROMs and RAMs