| Copyright | (C) 2017 Google Inc |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | None |
| Language | Haskell2010 |
Clash.Intel.DDR
Description
DDR primitives for Intel FPGAs using ALTDDIO primitives.
For general information about DDR primitives see Clash.Explicit.DDR.
Note that a synchronous reset is only available on certain devices, see ALTDDIO userguide for the specifics: https:/www.altera.comcontentdamaltera-wwwglobalen_USpdfsliteratureugug_altddio.pdf
Synopsis
- altddioIn :: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast), KnownNat m) => SSymbol deviceFamily -> Clock slow gated -> Reset slow synchronous -> Signal fast (BitVector m) -> Signal slow (BitVector m, BitVector m)
- altddioOut :: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast), KnownNat m) => SSymbol deviceFamily -> Clock slow gated -> Reset slow synchronous -> Signal slow (BitVector m, BitVector m) -> Signal fast (BitVector m)
Documentation
Arguments
| :: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast), KnownNat m) | |
| => SSymbol deviceFamily | The FPGA family For example this can be instantiated as follows: SSymbol @"Cyclone IV GX" |
| -> Clock slow gated | clock |
| -> Reset slow synchronous | reset |
| -> Signal fast (BitVector m) | DDR input signal |
| -> Signal slow (BitVector m, BitVector m) | normal speed output pairs |
Intel specific variant of ddrIn implemented using the ALTDDIO_IN IP core.
Reset values are 0
Arguments
| :: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast), KnownNat m) | |
| => SSymbol deviceFamily | The FPGA family For example this can be instantiated as follows: SSymbol @"Cyclone IV E" |
| -> Clock slow gated | clock |
| -> Reset slow synchronous | reset |
| -> Signal slow (BitVector m, BitVector m) | normal speed input pair |
| -> Signal fast (BitVector m) | DDR output signal |
Intel specific variant of ddrOut implemented using the ALTDDIO_OUT IP core.
Reset value is 0