Copyright | (C) 2015-2016, University of Twente |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
Safe Haskell | Safe |
Language | Haskell2010 |
Extensions |
|
RAM primitives with a combinational read port.
- asyncRam :: Enum addr => SNat n -> Signal addr -> Signal addr -> Signal Bool -> Signal a -> Signal a
- asyncRamPow2 :: forall n a. (KnownNat (2 ^ n), KnownNat n) => Signal (Unsigned n) -> Signal (Unsigned n) -> Signal Bool -> Signal a -> Signal a
- asyncRam' :: Enum addr => SClock wclk -> SClock rclk -> SNat n -> Signal' wclk addr -> Signal' rclk addr -> Signal' wclk Bool -> Signal' wclk a -> Signal' rclk a
- asyncRamPow2' :: forall wclk rclk n a. (KnownNat n, KnownNat (2 ^ n)) => SClock wclk -> SClock rclk -> Signal' wclk (Unsigned n) -> Signal' rclk (Unsigned n) -> Signal' wclk Bool -> Signal' wclk a -> Signal' rclk a
- asyncRam# :: SClock wclk -> SClock rclk -> SNat n -> Signal' wclk Int -> Signal' rclk Int -> Signal' wclk Bool -> Signal' wclk a -> Signal' rclk a
RAM synchronised to the system clock
:: Enum addr | |
=> SNat n | Size |
-> Signal addr | Write address |
-> Signal addr | Read address |
-> Signal Bool | Write enable |
-> Signal a | Value to write (at address |
-> Signal a | Value of the |
Create a RAM with space for n
elements.
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See CLaSH.Prelude.BlockRam for more information on how to use a RAM.
:: (KnownNat (2 ^ n), KnownNat n) | |
=> Signal (Unsigned n) | Write address |
-> Signal (Unsigned n) | Read address |
-> Signal Bool | Write enable |
-> Signal a | Value to write (at address |
-> Signal a | Value of the |
Create a RAM with space for 2^n
elements
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See CLaSH.Prelude.BlockRam for more information on how to use a RAM.
RAM synchronised to an arbitrary clock
:: Enum addr | |
=> SClock wclk |
|
-> SClock rclk |
|
-> SNat n | Size |
-> Signal' wclk addr | Write address |
-> Signal' rclk addr | Read address |
-> Signal' wclk Bool | Write enable |
-> Signal' wclk a | Value to write (at address |
-> Signal' rclk a | Value of the |
Create a RAM with space for n
elements
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See CLaSH.Prelude.BlockRam for more information on how to use a RAM.
:: (KnownNat n, KnownNat (2 ^ n)) | |
=> SClock wclk |
|
-> SClock rclk |
|
-> Signal' wclk (Unsigned n) | Write address |
-> Signal' rclk (Unsigned n) | Read address |
-> Signal' wclk Bool | Write enable |
-> Signal' wclk a | Value to write (at address |
-> Signal' rclk a | Value of the |
Create a RAM with space for 2^n
elements
- NB: Initial content of the RAM is
undefined
Additional helpful information:
- See CLaSH.Prelude.BlockRam for more information on how to use a RAM.
Internal
:: SClock wclk |
|
-> SClock rclk |
|
-> SNat n | Size |
-> Signal' wclk Int | Write address |
-> Signal' rclk Int | Read address |
-> Signal' wclk Bool | Write enable |
-> Signal' wclk a | Value to write (at address |
-> Signal' rclk a | Value of the |
RAM primitive